Current Issue : July - September Volume : 2017 Issue Number : 3 Articles : 5 Articles
Presented in this paper is a method for the design of modular reconfigurable machine tools\n(MRMTs). An MRMT is capable of using a minimal number of modules through reconfiguration\nto perform the required machining tasks for a family of parts. The proposed method consists of\nthree steps: module identification, module determination, and layout synthesis. In the first step, the\nmodule components are collected from a family of general-purpose machines to establish a module\nlibrary. In the second step, for a given family of parts to be machined, a set of needed modules are\nselected from the module library to construct a desired reconfigurable machine tool. In the third step,\na final machine layout is decided though evaluation by considering a number of performance indices.\nBased on this method, a software package has been developed that can design an MRMT for a given\npart family....
(Received 29 September 2016; accepted 24 December 2016; published online 11 January 2017)\nA highly integrated, high performance, and re-configurable device, which is designed for the\nNitrogen-Vacancy (N-V) center based quantum applications, is reported. The digital compartment of\nthe device is fully implemented in a Field-Programmable-Gate-Array (FPGA). The digital compartment\nis designed to manage the multi-function digital waveform generation and the time-to-digital\nconvertors. The device provides two arbitrary-waveform-generator channels which operate at a\n1 Gsps sampling rate with a maximum bandwidth of 500 MHz. There are twelve pulse channels\nintegrated in the device with a 50 ps time resolution in both duration and delay. The pulse channels\noperate with the 3.3 V transistor-transistor logic. The FPGA-based time-to-digital convertor provides\na 23-ps time measurement precision. A data accumulation module, which can record the input count\nrate and the distributions of the time measurement, is also available. A digital-to-analog convertor\nboard is implemented as the analog compartment, which converts the digital waveforms to analog\nsignals with 500 MHz lowpass filters. All the input and output channels of the device are equipped\nwith 50 �© SubMiniature version A termination. The hardware design is modularized thus it can be\neasily upgraded with compatible components. The device is suitable to be applied in the quantum\ntechnologies based on the N-V centers, as well as in other quantum solid state systems, such as\nquantum dots, phosphorus doped in silicon, and defect spins in silicon carbide....
Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several\ntechnological and scientific areas such as synthetic aperture radar, computational photography,\nmedical imaging, telecommunications, seismic analysis and so on. However, its computation\ncomplexity is high. In this paper, we describe an efficient NFFT implementation with a hardware\ncoprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that\nemploys an Advanced RISC Machine (ARM) as Processing System with Programmable Logic\nfor high-performance digital signal processing through parallelism and pipeline techniques.\nThe algorithm has been coded in C language with pragma directives to optimize the architecture of\nthe system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool\nthat simplifies the interface and partitioning between hardware and software. This provides shorter\ndevelopment cycles and iterative improvements by exploring several architectures of the global\nsystem. The computational results shows that hardware acceleration significantly outperformed the\nsoftware based implementation....
In this paper, a novel BCD multiplier approach is proposed. The main highlight of the proposed architecture is the generation of\nthe partial products and parallel binary operations based on 2-digit columns. 1 Ã?â?? 1-digit multipliers used for the partial product\ngeneration are implemented directly by 4-bit binary multipliers without any code conversion. The binary results of the 1 Ã?â?? 1-digit\nmultiplications are organized according to their two-digit positions to generate the 2-digit column-based partial products.Abinarydecimal\ncompressor structure is developed and used for partial product reduction. These reduced partial products are added in\noptimized 6-LUT BCD adders. The parallel binary operations and the improved BCD addition result in improved performance\nand reduced resource usage. The proposed approach was implemented on Xilinx Virtex-5 and Virtex-6 FPGAs with emphasis on\nthe critical path delay reduction. Pipelined BCD multipliers were implemented for 4 Ã?â?? 4, 8 Ã?â?? 8, and 16 Ã?â?? 16-digit multipliers. Our\nrealizations achieve an increase in speed by up to 22% and a reduction of LUT count by up to 14% over previously reported results....
In this paper, the design and the implementation of a pipelined hardware accelerator based on a fuzzy logic approach for an\nedge detection system are presented. The fuzzy system comprises a preprocessing stage, a fuzzifier with four fuzzy inputs, an\ninference system with seven rules, and a defuzzification stage delivering a single crisp output, which represents the intensity\nvalue of a pixel in the output image. The hardware accelerator consists of seven stages with one clock cycle latency per stage. The\ndefuzzification stage was implemented using three different defuzzification methods. These methods are the mean of maxima, the\nsmallest of maxima, and the largest of maxima.Thedefuzzification modules are interchangeable while the system runs using partial\nreconfiguration design methodology. System development was carried out usingVivadoHigh-Level Synthesis,VivadoDesign Suite,\nVivado Simulator, and a set ofXilinx 7000 FPGA devices.Depending upon the speed grade of the device that is employed, the system\ncan operate at a frequency range from 83MHz to 125MHz. Its peak performance is up to 58 high definition frames per second. A\ncomparison of this system�s performance and its software counterpart shows a significant speedup in the magnitude of hundred\nthousand times....
Loading....